dcc395208198eac4376418280e9e3ac9306fe3b4
2 * Copyright (c) 2017 Thomas Pornin <pornin@bolet.org>
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 * This code contains the AES key schedule implementation using the
35 #include <wmmintrin.h>
45 br_aes_x86ni_supported(void)
48 * Bit mask for features in ECX:
49 * 19 SSE4.1 (used for _mm_insert_epi32(), for AES-CTR)
52 #define MASK 0x02080000
55 unsigned eax
, ebx
, ecx
, edx
;
57 if (__get_cpuid(1, &eax
, &ebx
, &ecx
, &edx
)) {
58 return (ecx
& MASK
) == MASK
;
62 #elif BR_AES_X86NI_MSC
66 return ((uint32_t)info
[2] & MASK
) == MASK
;
76 expand_step128(__m128i k
, __m128i k2
)
78 k
= _mm_xor_si128(k
, _mm_slli_si128(k
, 4));
79 k
= _mm_xor_si128(k
, _mm_slli_si128(k
, 4));
80 k
= _mm_xor_si128(k
, _mm_slli_si128(k
, 4));
81 k2
= _mm_shuffle_epi32(k2
, 0xFF);
82 return _mm_xor_si128(k
, k2
);
87 expand_step192(__m128i
*t1
, __m128i
*t2
, __m128i
*t3
)
91 *t2
= _mm_shuffle_epi32(*t2
, 0x55);
92 t4
= _mm_slli_si128(*t1
, 0x4);
93 *t1
= _mm_xor_si128(*t1
, t4
);
94 t4
= _mm_slli_si128(t4
, 0x4);
95 *t1
= _mm_xor_si128(*t1
, t4
);
96 t4
= _mm_slli_si128(t4
, 0x4);
97 *t1
= _mm_xor_si128(*t1
, t4
);
98 *t1
= _mm_xor_si128(*t1
, *t2
);
99 *t2
= _mm_shuffle_epi32(*t1
, 0xFF);
100 t4
= _mm_slli_si128(*t3
, 0x4);
101 *t3
= _mm_xor_si128(*t3
, t4
);
102 *t3
= _mm_xor_si128(*t3
, *t2
);
105 BR_TARGET("sse2,aes")
107 expand_step256_1(__m128i
*t1
, __m128i
*t2
)
111 *t2
= _mm_shuffle_epi32(*t2
, 0xFF);
112 t4
= _mm_slli_si128(*t1
, 0x4);
113 *t1
= _mm_xor_si128(*t1
, t4
);
114 t4
= _mm_slli_si128(t4
, 0x4);
115 *t1
= _mm_xor_si128(*t1
, t4
);
116 t4
= _mm_slli_si128(t4
, 0x4);
117 *t1
= _mm_xor_si128(*t1
, t4
);
118 *t1
= _mm_xor_si128(*t1
, *t2
);
121 BR_TARGET("sse2,aes")
123 expand_step256_2(__m128i
*t1
, __m128i
*t3
)
127 t4
= _mm_aeskeygenassist_si128(*t1
, 0x0);
128 t2
= _mm_shuffle_epi32(t4
, 0xAA);
129 t4
= _mm_slli_si128(*t3
, 0x4);
130 *t3
= _mm_xor_si128(*t3
, t4
);
131 t4
= _mm_slli_si128(t4
, 0x4);
132 *t3
= _mm_xor_si128(*t3
, t4
);
133 t4
= _mm_slli_si128(t4
, 0x4);
134 *t3
= _mm_xor_si128(*t3
, t4
);
135 *t3
= _mm_xor_si128(*t3
, t2
);
139 * Perform key schedule for AES, encryption direction. Subkeys are written
140 * in sk[], and the number of rounds is returned. Key length MUST be 16,
143 BR_TARGET("sse2,aes")
145 x86ni_keysched(__m128i
*sk
, const void *key
, size_t len
)
147 const unsigned char *kb
;
149 #define KEXP128(k, i, rcon) do { \
150 k = expand_step128(k, _mm_aeskeygenassist_si128(k, rcon)); \
154 #define KEXP192(i, rcon1, rcon2) do { \
157 t2 = _mm_aeskeygenassist_si128(t3, rcon1); \
158 expand_step192(&t1, &t2, &t3); \
159 sk[(i) + 1] = _mm_castpd_si128(_mm_shuffle_pd( \
160 _mm_castsi128_pd(sk[(i) + 1]), \
161 _mm_castsi128_pd(t1), 0)); \
162 sk[(i) + 2] = _mm_castpd_si128(_mm_shuffle_pd( \
163 _mm_castsi128_pd(t1), \
164 _mm_castsi128_pd(t3), 1)); \
165 t2 = _mm_aeskeygenassist_si128(t3, rcon2); \
166 expand_step192(&t1, &t2, &t3); \
169 #define KEXP256(i, rcon) do { \
171 t2 = _mm_aeskeygenassist_si128(t3, rcon); \
172 expand_step256_1(&t1, &t2); \
174 expand_step256_2(&t1, &t3); \
182 t1
= _mm_loadu_si128((const void *)kb
);
184 KEXP128(t1
, 1, 0x01);
185 KEXP128(t1
, 2, 0x02);
186 KEXP128(t1
, 3, 0x04);
187 KEXP128(t1
, 4, 0x08);
188 KEXP128(t1
, 5, 0x10);
189 KEXP128(t1
, 6, 0x20);
190 KEXP128(t1
, 7, 0x40);
191 KEXP128(t1
, 8, 0x80);
192 KEXP128(t1
, 9, 0x1B);
193 KEXP128(t1
, 10, 0x36);
197 t1
= _mm_loadu_si128((const void *)kb
);
198 t3
= _mm_loadu_si128((const void *)(kb
+ 8));
199 t3
= _mm_shuffle_epi32(t3
, 0x4E);
200 KEXP192(0, 0x01, 0x02);
201 KEXP192(3, 0x04, 0x08);
202 KEXP192(6, 0x10, 0x20);
203 KEXP192(9, 0x40, 0x80);
208 t1
= _mm_loadu_si128((const void *)kb
);
209 t3
= _mm_loadu_si128((const void *)(kb
+ 16));
218 t2
= _mm_aeskeygenassist_si128(t3
, 0x40);
219 expand_step256_1(&t1
, &t2
);
233 BR_TARGET("sse2,aes")
235 br_aes_x86ni_keysched_enc(unsigned char *skni
, const void *key
, size_t len
)
240 num_rounds
= x86ni_keysched(sk
, key
, len
);
241 memcpy(skni
, sk
, (num_rounds
+ 1) << 4);
246 BR_TARGET("sse2,aes")
248 br_aes_x86ni_keysched_dec(unsigned char *skni
, const void *key
, size_t len
)
251 unsigned u
, num_rounds
;
253 num_rounds
= x86ni_keysched(sk
, key
, len
);
254 _mm_storeu_si128((void *)skni
, sk
[num_rounds
]);
255 for (u
= 1; u
< num_rounds
; u
++) {
256 _mm_storeu_si128((void *)(skni
+ (u
<< 4)),
257 _mm_aesimc_si128(sk
[num_rounds
- u
]));
259 _mm_storeu_si128((void *)(skni
+ (num_rounds
<< 4)), sk
[0]);