Fixed computation of product size.
[BearSSL] / src / config.h
1 /*
2 * Copyright (c) 2016 Thomas Pornin <pornin@bolet.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #ifndef CONFIG_H__
26 #define CONFIG_H__
27
28 /*
29 * This file contains compile-time flags that can override the
30 * autodetection performed in relevant files. Each flag is a macro; it
31 * deactivates the feature if defined to 0, activates it if defined to a
32 * non-zero integer (normally 1). If the macro is not defined, then
33 * autodetection applies.
34 */
35
36 /*
37 * When BR_64 is enabled, 64-bit integer types are assumed to be
38 * efficient (i.e. the architecture has 64-bit registers and can
39 * do 64-bit operations as fast as 32-bit operations).
40 *
41 #define BR_64 1
42 */
43
44 /*
45 * When BR_LOMUL is enabled, then multiplications of 32-bit values whose
46 * result are truncated to the low 32 bits are assumed to be
47 * substantially more efficient than 32-bit multiplications that yield
48 * 64-bit results. This is typically the case on low-end ARM Cortex M
49 * systems (M0, M0+, M1, and arguably M3 and M4 as well).
50 *
51 #define BR_LOMUL 1
52 */
53
54 /*
55 * When BR_SLOW_MUL is enabled, multiplications are assumed to be
56 * substantially slow with regards to other integer operations, thus
57 * making it worth to make more operations for a given task if it allows
58 * using less multiplications.
59 *
60 #define BR_SLOW_MUL 1
61 */
62
63 /*
64 * When BR_SLOW_MUL15 is enabled, short multplications (on 15-bit words)
65 * are assumed to be substantially slow with regards to other integer
66 * operations, thus making it worth to make more integer operations if
67 * it allows using less multiplications.
68 *
69 #define BR_SLOW_MUL15 1
70 */
71
72 /*
73 * When BR_CT_MUL31 is enabled, multiplications of 31-bit values (used
74 * in the "i31" big integer implementation) use an alternate implementation
75 * which is slower and larger than the normal multiplication, but should
76 * ensure constant-time multiplications even on architectures where the
77 * multiplication opcode takes a variable number of cycles to complete.
78 *
79 #define BR_CT_MUL31 1
80 */
81
82 /*
83 * When BR_CT_MUL15 is enabled, multiplications of 15-bit values (held
84 * in 32-bit words) use an alternate implementation which is slower and
85 * larger than the normal multiplication, but should ensure
86 * constant-time multiplications on most/all architectures where the
87 * basic multiplication is not constant-time.
88 #define BR_CT_MUL15 1
89 */
90
91 /*
92 * When BR_NO_ARITH_SHIFT is enabled, arithmetic right shifts (with sign
93 * extension) are performed with a sequence of operations which is bigger
94 * and slower than a simple right shift on a signed value. This avoids
95 * relying on an implementation-defined behaviour. However, most if not
96 * all C compilers use sign extension for right shifts on signed values,
97 * so this alternate macro is disabled by default.
98 #define BR_NO_ARITH_SHIFT 1
99 */
100
101 /*
102 * When BR_RDRAND is enabled, the SSL engine will use the RDRAND opcode
103 * to automatically obtain quality randomness for seeding its internal
104 * PRNG. Since that opcode is present only in recent x86 CPU, its
105 * support is dynamically tested; if the current CPU does not support
106 * it, then another random source will be used, such as /dev/urandom or
107 * CryptGenRandom().
108 *
109 #define BR_RDRAND 1
110 */
111
112 /*
113 * When BR_USE_URANDOM is enabled, the SSL engine will use /dev/urandom
114 * to automatically obtain quality randomness for seedings its internal
115 * PRNG.
116 *
117 #define BR_USE_URANDOM 1
118 */
119
120 /*
121 * When BR_USE_WIN32_RAND is enabled, the SSL engine will use the Win32
122 * (CryptoAPI) functions (CryptAcquireContext(), CryptGenRandom()...) to
123 * automatically obtain quality randomness for seedings its internal PRNG.
124 *
125 * Note: if both BR_USE_URANDOM and BR_USE_WIN32_RAND are defined, the
126 * former takes precedence.
127 *
128 #define BR_USE_WIN32_RAND 1
129 */
130
131 /*
132 * When BR_USE_UNIX_TIME is enabled, the X.509 validation engine obtains
133 * the current time from the OS by calling time(), and assuming that the
134 * returned value (a 'time_t') is an integer that counts time in seconds
135 * since the Unix Epoch (Jan 1st, 1970, 00:00 UTC).
136 *
137 #define BR_USE_UNIX_TIME 1
138 */
139
140 /*
141 * When BR_USE_WIN32_TIME is enabled, the X.509 validation engine obtains
142 * the current time from the OS by calling the Win32 function
143 * GetSystemTimeAsFileTime().
144 *
145 * Note: if both BR_USE_UNIX_TIME and BR_USE_WIN32_TIME are defined, the
146 * former takes precedence.
147 *
148 #define BR_USE_WIN32_TIME 1
149 */
150
151 /*
152 * When BR_ARMEL_CORTEXM_GCC is enabled, some operations are replaced with
153 * inline assembly which is shorter and/or faster. This should be used
154 * only when all of the following are true:
155 * - target architecture is ARM in Thumb mode
156 * - target endianness is little-endian
157 * - compiler is GCC (or GCC-compatible for inline assembly syntax)
158 *
159 * This is meant for the low-end cores (Cortex M0, M0+, M1, M3).
160 * Note: if BR_LOMUL is not explicitly enabled or disabled, then
161 * enabling BR_ARMEL_CORTEXM_GCC also enables BR_LOMUL.
162 *
163 #define BR_ARMEL_CORTEXM_GCC 1
164 */
165
166 /*
167 * When BR_AES_X86NI is enabled, the AES implementation using the x86 "NI"
168 * instructions (dedicated AES opcodes) will be compiled. If this is not
169 * enabled explicitly, then that AES implementation will be compiled only
170 * if a compatible compiler is detected. If set explicitly to 0, the
171 * implementation will not be compiled at all.
172 *
173 #define BR_AES_X86NI 1
174 */
175
176 /*
177 * When BR_SSE2 is enabled, SSE2 intrinsics will be used for some
178 * algorithm implementations that use them (e.g. chacha20_sse2). If this
179 * is not enabled explicitly, then support for SSE2 intrinsics will be
180 * automatically detected. If set explicitly to 0, then SSE2 code will
181 * not be compiled at all.
182 *
183 #define BR_SSE2 1
184 */
185
186 /*
187 * When BR_POWER8 is enabled, the AES implementation using the POWER ISA
188 * 2.07 opcodes (available on POWER8 processors and later) is compiled.
189 * If this is not enabled explicitly, then that implementation will be
190 * compiled only if a compatible compiler is detected, _and_ the target
191 * architecture is POWER8 or later.
192 *
193 #define BR_POWER8 1
194 */
195
196 /*
197 * When BR_INT128 is enabled, then code using the 'unsigned __int64'
198 * and 'unsigned __int128' types will be used to leverage 64x64->128
199 * unsigned multiplications. This should work with GCC and compatible
200 * compilers on 64-bit architectures.
201 *
202 #define BR_INT128 1
203 */
204
205 /*
206 * When BR_UMUL128 is enabled, then code using the '_umul128()' and
207 * '_addcarry_u64()' intrinsics will be used to implement 64x64->128
208 * unsigned multiplications. This should work on Visual C on x64 systems.
209 *
210 #define BR_UMUL128 1
211 */
212
213 /*
214 * When BR_LE_UNALIGNED is enabled, then the current architecture is
215 * assumed to use little-endian encoding for integers, and to tolerate
216 * unaligned accesses with no or minimal time penalty.
217 *
218 #define BR_LE_UNALIGNED 1
219 */
220
221 /*
222 * When BR_BE_UNALIGNED is enabled, then the current architecture is
223 * assumed to use big-endian encoding for integers, and to tolerate
224 * unaligned accesses with no or minimal time penalty.
225 *
226 #define BR_BE_UNALIGNED 1
227 */
228
229 #endif